(a) Field of the Invention
The present invention relates to a non-volatile semiconductor storage device such as flash EEPROM, more in particular to the non-volatile semiconductor storage device having a function of selecting a group of word lines.
(b) Description of the Related Art
FIG. 1 is a circuit diagram showing a main part of a conventional EEPROM. This EEPROM has a plurality of non-volatile memory cells located at each intersection in the form of matrix formed by a plurality of word lines WL and a plurality of bit lines BL. The EEPROM has an X decoder 21 connected to each of the memory cells through the respective word lines WL extending in the row direction (horizontal direction in FIG. 1) and a column control circuit 22 connected to each of the memory cells through a selection line SL and the bit line BL perpendicular to the word line WL. The EEPROM further has a voltage establishing circuit 25 and a charge pump 23 providing a required voltage to the voltage establishing circuit 25.
A cell array CA has select transistors STr11 and STr12 and a cell transistor CTr11 constituting the memory cell. The word line WL is connected to each gate of the select transistors STr11 and STr12. The cell transistor CTr11 has a floating gate FG and a control gate CG. The select transistors STr11 and STr12 and the cell transistor CTr11 are formed by N-channel MOS transistors. The drain of the select transistor STr11 is connected to the selection line SL, and the source thereof is connected to the control gate CG of the cell transistor CTr11. The drain of the select transistor STr12 is connected to the bit line BL, and the source thereof is connected to the drain of the cell transistor CTr11 .
Although an example is shown in FIG. 1 wherein one cell transistor CTr11 is connected to one select transistor STr11, generally a plurality of the cell transistors CTr11 are connected to one select transistor STr11 thereby enabling collective reading and writing of a plurality of the cell transistors CTr11 by the selection line SL. Therefore, one selection line SL and a plurality of the bit lines BL are connected to one cell array CA and the number of the bit lines are, for example, between 8 and 32.
The X decoder 21 has a function of selecting the word line WL in accordance with a supplied address signal. The selection line SL from the column control circuit 22 is selected in accordance with a supplied address signal. The bit line BL from the column control circuit 22 outputs a signal only in reading operation and writing operation, and the logic level of the signal is determined by the writing value. During the reading operation, a reading voltage VR (about 1 V) is applied to the output of the bit line BL of the column control circuit 22, and the stored information of the output of the memory cell is judged by a sense amplifier SA and externally outputted. The output of the sense amplifier SA may be further selected by a column selection signal obtained by decoding the address signal.
The voltage establishing circuit 25 has a load circuit 26. The voltage establishing circuit 25 detects a program voltage VppH (for example, about 18 V) supplied from the charge pump 23 as an output voltage, and stops the operation of the charge pump when the voltage rises over a prescribed voltage and restarts the operation of the charge pump when the voltage decreases below the prescribed voltage. The voltage establishing circuit 25 supplies the program voltage VppH to the X decoder 21 and the column control circuit 22.
FIG. 2 is a table showing states of voltages applied to each of the nodes under the respective modes of writing, collective erasing and ordinary reading. The operation of the above conventional EEPROM is described in accordance with FIG. 2.
When "1") is written in the cell transistor CTr11, the select transistors STr11 and STr12 of the selected memory cell are turned on after each gate is biased to the program voltage VppH through the word line WL. Since the column control circuit 22 biases the drain of the select transistor STr11 to 0 V through the selection line SL, the control gate CG of the cell transistor CTr11 is biased to 0V. Since the column control circuit 22 simultaneously biases the drain of the select transistor STr12 to the program voltage VppH through the bit line BL, VppL (for example, about 15 V) obtained by subtracting a forward direction voltage drop from the program voltage VppH applied to the gate is applied to the source of the select transistor STr12. The drain of the cell transistor CTr11 is biased to the program voltage VppL, and the writing is performed by extracting electric charges from the floating gate FG. Since both of the selection line SL and the bit line BL are biased to 0V when the "0" is written in the cell transistor CTr11, the control gate CG and the drain of the cell transistor CTr11 become 0V. Accordingly, no electric charge is extracted from the floating gate FG and the erase state "0" is maintained. This is also applicable to the non-selected cell transistor CTr11.
When a plurality of the cell transistors CTr11 connected to one select transistor STr11 are collectively erased, the select transistors STr11 and STr12 in the selected memory cell are turned on by biasing each of the gates are biased to the program voltage VppH through the word lines WL. Since in this stage the column control circuit 22 biases the drain of the select transistor STr11 to the program voltage VppH through the selection line SL, the program voltage VppL is applied to the source of the select transistor STr11 in accordance with a similar principle. Thereby, the control gate of the cell transistor CTr11 is biased to the program voltage VppL. Since the column control circuit 22 biases the drain of the select transistor STr12 to 0V through the bit line BL, the drain of the cell transistor CTr11 is biased to 0V through the select transistor STr12. Thereby, electric charges are poured into the floating gate FG of the cell transistor CTr11 to perform the collective erasing. In the non-selected cell array CA, either of the selection line SL or the word line WL is 0V and the bit line BL is also 0V so that no erasing operation occurs.
FIG. 3 is a block diagram showing the column control circuit 22 in detail. The column control circuit 22 is composed of a plurality of switching circuits 221 to 223 and a voltage changing switch 224 in FIG. 3. Each of the switching circuits 221 to 223 has terminals (a), (b) and (c). A power supply voltage V.sub.R or the program voltage VppH is supplied to the respective terminals (a). The respective terminals (b) are connected to the selection line SL, or the bit line BL0, BLn. Keying signals C.sub.1 to C.sub.3 for the switching circuits are inputted to the respective terminals (c). The voltage changing switch 224 changes the power supply voltage V.sub.R with the program voltage VppH or vice versa.
The keying signal C.sub.1 controlling the selection line SL is a signal obtained by decoding an address signal supplied by a column control circuit (not shown). The keying signals C.sub.2 and C.sub.3 controlling the bit lines BL0 to BLn are logical product signals of a mode signal for a writing operation/an erasing operation and of a writing value or an erasing value. The terminal (b) outputs VppH/VR when the keying signals C.sub.1 to C.sub.3 are "1" and outputs 0V when the keying signals C.sub.1 to C.sub.3 are "0". The number of the switching circuits 222, 223 accommodated in one column control circuit 22 is determined by the constitution of the nonvolatile semiconductor storage. For example, the number is between 8 and 32, and amounts to several hundreds in the whole device.
FIG. 4 is a detail circuit diagram showing the switching circuit 221 to 223. Each of the switching circuits 221 to 223 (FIG. 3) consists of transistors Tr15 and Tr16 which are P-channel MOS transistors (hereinafter referred to as PMOS transistor(s)), transistors Tr17 and Tr18 which are N-channel MOS transistors (hereinafter referred to as NMOS transistor(s)) and a complementary circuit (flip-flop circuit) having an inverter 11, and functions as a level shifter.
The transistor Tr15 has a source (terminal (a)) to which the power supply voltage V.sub.R or the program voltage VppH is supplied, a drain which is connected to a drain of the transistor Tr17 and a gate which is connected to a drain of the transistor Tr18. The transistor Tr16 has a source (terminal (a)) to which the power supply voltage V.sub.R or the program voltage VppH is supplied, a drain which is connected to the drain of the transistor Tr18 and a gate which is connected to the drain of the transistor Tr17. The transistor Tr17 has a grounded source and a gate which is connected to an input of the inverter 11. The transistor Tr18 has a grounded source and a gate which is connected to an output of the inverter 11. An output V.sub.01 is extracted from a common connection point among the drain of the transistor Tr15, the drain of the transistor TR17 and the gate of the transistor Tr16, and an output V.sub.02 is extracted from a common connection point (terminal (b)) among the drain of the transistor Tr16, the drain of the transistor TR18 and the gate of the transistor Tr15. A HIGH signal of 5V or a LOW signal of 0V is selectively inputted to the input Ci (terminal (c)) of the inverter.
The switching circuits 221 to 223 having the above constitutions operate as follows. When a HIGH signal is inputted to the input of the inverter 11 as a keying signal Ci, a HIGH signal is applied to the gate of the transistor Tr17 to turn on the transistor Tr17 and to make its drain (V.sub.01) LOW. A LOW signal is applied to the gate of the transistor Tr18 to turn off the transistor Tr18. Thereby, a LOW signal is applied to the gate of the transistor Tr16 to turn on the transistor Tr16 to make the drain (V.sub.02) of the transistor Tr16 HIGH. Simultaneously, a HIGH signal is applied to the gate of the transistor Tr15 to turn off the transistor Tr15. Thereby, the program voltage VppH is supplied to V.sub.02, and this program voltage VppH is extracted as an output V.sub.02.
When, on the other hand, a LOW signal is inputted to the input of the inverter 11 as the keying signal Ci, a HIGH signal is applied to the gate of the transistor Tr18 to turn on the transistor Tr18 and to make V.sub.02 LOW. A LOW signal is applied to the gate of the transistor Tr17 to turn off the transistor Tr17. Thereby, a LOW signal is applied to the gate of the transistor Tr15 to turn on the transistor Tr15 and to make V.sub.01 HIGH. As a result, a HIGH signal is applied to the gate of the transistor Tr16 to turn off the transistor Tr16 and to make V.sub.02 LOW. In this manner, V.sub.02 is selectively supplied to the selection line SL or the bit line BL of the selected cell array CA.
As mentioned, although the program voltage VppL is sufficient even for the higher voltage supplied to the cell transistor CTr11 in the conventional EEPROM, VppH higher than the program voltage VppL is supplied to the select transistors STr11 and STr12. Due to this, a transistor having a higher drain-source withstand voltage must be employed as the select transistors STr11 and STr12. Therefore, the drain-source distance increases to make the occupied areas of the select transistors STr11 and STr12 larger. Since the column control circuit 22 supplies the program voltage VppH higher than required to the respective drains of the select transistors STr11 and STr12, transistors having larger occupied areas must be employed to elevate withstand voltages so that a large-scale EEPROM must be used.
The four transistors Tr15 to Tr18 constituting the switching circuits 221 to 223 require a source-drain withstand voltage higher than the program voltage VppH. For example, since the transistors Tr15 and Tr18 turns on when the keying signal Ci is "0", the program voltage VppH is applied to the point between the source and the drain of the transistors Tr16 and Tr17. Vice versa, when the keying signal Ci is "1", the program voltage VppH is applied to the point between the source and the drain of the transistors Tr15 and Tr18. Accordingly, the respective source-drain withstand voltages of the above four transistors Tr15 to Tr18 are required to be higher than the program voltage VppH.
As mentioned, several hundreds of the switching circuits 221 to 223 exist in the whole device, and the number of the transistors Tr15 to Tr18 amounts to 1000 or more because it is four times as many as that of the switching circuits. Even if the occupied area increase per one transistor is slight, the large increase is produced in the whole device. It is a difficult problem how to reduce the area occupied by a large number of transistors.
It is known to relatively reduce a voltage applied to the column control circuit by forming a negative voltage power supply. However, in this instance, the number of auxiliary circuits increases. For example, a charge pump circuit generating a negative charge is required in addition to a charge pump circuit generating a positive charge, or a special circuit changing a positive voltage and a negative voltage is needed. Since, further, the positive voltage and the negative voltage are generated in the same transistor, the number of steps for manufacturing the transistor increases and the transistor must be designed considering the control of a voltage in a well region.